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| MCP3204/3208 2.7V 4-Channel/8-Channel 12-Bit A/D Converters with SPI Serial Interface Features * * * * * * * * * * * * 12-bit resolution 1 LSB max DNL 1 LSB max INL (MCP3204/3208-B) 2 LSB max INL (MCP3204/3208-C) 4 (MCP3204) or 8 (MCP3208) input channels Analog inputs programmable as single-ended or pseudo-differential pairs On-chip sample and hold SPI serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V - 5.5V 100 ksps max. sampling rate at VDD = 5V 50 ksps max. sampling rate at VDD = 2.7V Low power CMOS technology: - 500 nA typical standby current, 2 A max. - 400 A max. active current at 5V Industrial temp range: -40C to +85C Available in PDIP, SOIC and TSSOP packages Description The Microchip Technology Inc. MCP3204/3208 devices are successive approximation 12-bit Analogto-Digital (A/D) Converters with on-board sample and hold circuitry. The MCP3204 is programmable to provide two pseudo-differential input pairs or four single-ended inputs. The MCP3208 is programmable to provide four pseudo-differential input pairs or eight single-ended inputs. Differential Nonlinearity (DNL) is specified at 1 LSB, while Integral Nonlinearity (INL) is offered in 1 LSB (MCP3204/3208-B) and 2 LSB (MCP3204/3208-C) versions. Communication with the devices is accomplished using a simple serial interface compatible with the SPI protocol. The devices are capable of conversion rates of up to 100 ksps. The MCP3204/3208 devices operate over a broad voltage range (2.7V - 5.5V). Low current design permits operation with typical standby and active currents of only 500 nA and 320 A, respectively. The MCP3204 is offered in 14-pin PDIP, 150 mil SOIC and TSSOP packages. The MCP3208 is offered in 16-pin PDIP and SOIC packages. * * Applications * * * * Sensor Interface Process Control Data Acquisition Battery Operated Systems Package Types PDIP, SOIC, TSSOP CH0 CH1 CH2 CH3 NC NC DGND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD VREF AGND CLK DOUT DIN CS/SHDN MCP3204 Functional Block Diagram VREF CH0 CH1 CH7* Sample and Hold Control Logic CS/SHDN DIN CLK Input Channel Mux VDD VSS PDIP, SOIC DAC Comparator 12-Bit SAR CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VREF AGND CLK DOUT DIN CS/SHDN DGND MCP3208 Shift Register DOUT * Note: Channels 5-7 available on MCP3208 Only (c) 2008 Microchip Technology Inc. DS21298E-page 1 MCP3204/3208 1.0 ELECTRICAL CHARACTERISTICS Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings VDD...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VDD +0.6V Storage temperature .....................................-65C to +150C Ambient temp. with power applied ................-65C to +125C Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all pins.............................................> 4 kV ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TA = -40C to +85C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE Parameters Conversion Rate Conversion Time Analog Input Sample Time Throughput Rate DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Dynamic Performance Total Harmonic Distortion Signal to Noise and Distortion (SINAD) Spurious Free Dynamic Range Reference Input Voltage Range Current Drain Analog Inputs Input Voltage Range for CH0CH7 in Single-Ended Mode VSS -- VREF V 0.25 -- -- -- 100 0.001 VDD 150 3.0 V A A Note 2 CS = VDD = 5V -- -- -- -82 72 86 -- -- -- dB dB dB VIN = 0.1V to 4.9V@1 kHz VIN = 0.1V to 4.9V@1 kHz VIN = 0.1V to 4.9V@1 kHz INL DNL -- -- -- -- -- 12 0.75 1.0 0.5 1.25 1.25 1 2 1 3 5 bits LSB LSB LSB LSB MCP3204/3208-B MCP3204/3208-C No missing codes over-temperature tCONV tSAMPLE fSAMPLE -- -- -- -- 1.5 -- -- 100 50 12 clock cycles clock cycles ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V Sym Min Typ Max Units Conditions Input Voltage Range for IN+ in IN-- VREF+INpseudo-differential Mode Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, particularly at elevated temperatures. See Section 6.2 "Maintaining Minimum Clock Speed", "Maintaining Minimum Clock Speed", for more information. DS21298E-page 2 (c) 2008 Microchip Technology Inc. MCP3204/3208 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TA = -40C to +85C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE Parameters Input Voltage Range for IN- in pseudo-differential Mode Leakage Current Switch Resistance Sample Capacitor Digital Input/Output Data Coding Format High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance (All Inputs/Outputs) Timing Parameters Clock Frequency Clock High Time Clock Low Time CS Fall To First Rising CLK Edge Data Input Setup Time Data Input Hold Time CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time Power Requirements Operating Voltage Operating Current Standby Current Note 1: 2: 3: VDD IDD IDDS 2.7 -- -- -- -- 320 225 0.5 5.5 400 -- 2.0 V A A VDD=VREF = 5V, DOUT unloaded VDD=VREF = 2.7V, DOUT unloaded CS = VDD = 5.0V fCLK tHI tLO tSUCS tSU tHD tDO tEN tDIS tCSH tR tF -- -- 250 250 100 50 50 -- -- -- 500 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 1.0 -- -- -- -- -- 200 200 100 -- 100 100 MHz MHz ns ns ns ns ns ns ns ns ns ns ns See Figures 1-2 and 1-3 (Note 1) See Figures 1-2 and 1-3 (Note 1) See Figures 1-2 and 1-3 See Figures 1-2 and 1-3 See Figures 1-2 and 1-3 VDD = 5V (Note 3) VDD = 2.7V (Note 3) VIH VIL VOH VOL ILI ILO CIN,COUT -- 4.1 -- -10 -10 -- Straight Binary 0.7 VDD -- -- -- -- -- -- -- -- 0.3 VDD -- 0.4 10 10 10 V V V V A A pF IOH = -1 mA, VDD = 4.5V IOL = 1 mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD VDD = 5.0V (Note 1) TA = 25C, f = 1 MHz Sym Min VSS-100 -- -- -- Typ -- 0.001 1000 20 Max VSS+100 1 -- -- Units mV A pF See Figure 4-1 See Figure 4-1 Conditions This parameter is established by characterization and not 100% tested. See graphs that relate linearity performance to VREF levels. Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, particularly at elevated temperatures. See Section 6.2 "Maintaining Minimum Clock Speed", "Maintaining Minimum Clock Speed", for more information. (c) 2008 Microchip Technology Inc. DS21298E-page 3 MCP3204/3208 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 5V Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Thermal Resistance, 16L-PDIP Thermal Resistance, 16L-SOIC JA JA JA JA JA -- -- -- -- -- 70 95.3 100 70 86.1 -- -- -- -- -- C/W C/W C/W C/W C/W tCSH CS Sym TA TA TA Min -40 -40 -65 Typ -- -- -- Max +125 +125 +150 Units C C C Conditions tSUCS tHI tLO CLK tSU DIN tHD MSB IN tEN tDO Null Bit MSB OUT tR tF tDIS LSB DOUT FIGURE 1-1: Serial Interface Timing. DS21298E-page 4 (c) 2008 Microchip Technology Inc. MCP3204/3208 1.4V 3 k DOUT CL = 100 pF Test Point VDD Test Point DOUT 100 pF VSS 3 k VDD/2 tDIS Waveform 2 tEN Waveform tDIS Waveform 1 Voltage Waveforms for tR, tF DOUT tR tF CLK Voltage Waveforms for tDO DOUT CLK tDO DOUT VOH VOL CS Voltage Waveforms for tEN 1 2 3 4 B11 tEN Voltage Waveforms for tDIS CS VIH 90% TDIS DOUT Waveform 2 * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. 10% FIGURE 1-2: Load Circuit for tR, tF, tDO. DOUT Waveform 1* FIGURE 1-3: Load circuit for tDIS and tEN. (c) 2008 Microchip Technology Inc. DS21298E-page 5 MCP3204/3208 NOTES: DS21298E-page 6 (c) 2008 Microchip Technology Inc. MCP3204/3208 2.0 Note: TYPICAL PERFORMANCE CHARACTERISTICS The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25C. 1.0 0.8 0.6 0.4 Positive INL 2.0 1.5 1.0 VDD = VREF = 2.7 V Positive INL INL (LSB) INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 50 75 100 125 150 Negative INL 0.5 0.0 Negative INL -0.5 -1.0 -1.5 -2.0 0 10 20 30 40 50 60 70 80 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-1: vs. Sample Rate. Integral Nonlinearity (INL) FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). 2.5 2.0 1.5 2.0 1.5 1.0 Positive INL Positive INL INL (LSB) 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 1 INL (LSB) 0.5 0.0 -0.5 -1.0 -1.5 Negative INL Negative INL 2 3 4 5 -2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VREF (V) VREF (V) FIGURE 2-2: vs. VREF . 1.0 0.8 0.6 Integral Nonlinearity (INL) FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF (VDD = 2.7V). 1.0 0.8 0.6 VDD = VREF = 2.7 V FSAMPLE = 50 ksps INL (LSB) INL (LSB) 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code Digital Code FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). (c) 2008 Microchip Technology Inc. DS21298E-page 7 MCP3204/3208 Note: Unless otherwise indicated, VDD = VREF = 5 V, VSS = 0 V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25C. 1.0 0.8 0.6 0.4 Positive INL 1.0 0.8 0.6 0.4 Positive INL VDD = VREF = 2.7 V FSAMPLE = 50 ksps INL (LSB) INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 Negative INL 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 Negative INL Temperature (C) Temperature (C) FIGURE 2-7: vs. Temperature. 1.0 0.8 0.6 Integral Nonlinearity (INL) FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V). 2.0 VDD = VREF = 2.7 V 1.5 1.0 DNL (LSB) DNL (LSB) 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 50 75 100 125 150 Negative DNL Positive DNL 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 10 20 30 40 50 60 70 80 Positive DNL Negative DNL Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate. FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V). 3.0 2.0 3.0 2.0 Positive DNL VDD = VREF = 2.7 V FSAMPLE = 50 ksps Positive DNL DNL (LSB) 0.0 -1.0 -2.0 -3.0 0 1 2 3 4 5 Negative DNL DNL (LSB) 1.0 1.0 0.0 -1.0 -2.0 -3.0 0.0 0.5 Negative DNL 1.0 1.5 2.0 2.5 3.0 VREF (V) VREF (V) FIGURE 2-9: (DNL) vs. VREF . Differential Nonlinearity FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF (VDD = 2.7V). DS21298E-page 8 (c) 2008 Microchip Technology Inc. MCP3204/3208 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25C. 1.0 0.8 0.6 1.0 0.8 0.6 VDD = VREF = 2.7 V FSAMPLE = 50 ksps DNL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 DNL (LSB) 0.4 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code Digital Code FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part). FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V). 1.0 0.8 0.6 VDD = VREF = 2.7 V FSAMPLE = 50 ksps Positive DNL 1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0.0 DNL (LSB) Positive DNL 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 Negative DNL Negative DNL -50 -25 0 25 50 75 100 Temperature (C) Temperature (C) FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature. FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V). 4 3 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 0 1 2 3 4 5 VDD = VREF = 2.7V FSAMPLE = 50 ksps VDD = VREF = 5V FSAMPLE = 100 ksps 2 1 0 -1 -2 -3 -4 VDD = VREF = 5 V FSAMPLE = 100 ksps VREF (V) Offset Error (LSB) Gain Error (LSB) VREF (V) FIGURE 2-15: Gain Error vs. VREF . FIGURE 2-18: Offset Error vs. VREF . (c) 2008 Microchip Technology Inc. DS21298E-page 9 MCP3204/3208 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25C. 0.2 0.0 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 2.0 1.8 VDD = VREF = 5 V FSAMPLE = 100 ksps Offset Error (LSB) Gain Error (LSB) -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -50 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 VDD = VREF = 5 V FSAMPLE = 100 ksps VDD = VREF = 2.7 V FSAMPLE = 50 ksps -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (C) Temperature (C) FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Temperature. 100 Offset Error vs. 100 90 80 70 60 50 40 30 20 10 0 1 10 100 VDD = VREF = 2.7V FSAMPLE = 50 ksps VDD = VREF = 5 V FSAMPLE = 100 ksps 90 80 VDD = VREF = 5 V FSAMPLE = 100 ksps SFDR (dB) 70 60 50 40 30 20 10 0 1 10 100 VDD = VREF = 2.7 V FSAMPLE = 50 ksps SNR (dB) Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-20: Input Frequency. 0 -10 -20 -30 Signal-to-Noise (SNR) vs. FIGURE 2-23: Signal-to-Noise and Distortion (SINAD) vs. Input Frequency. 80 70 VDD = VREF = 2.7V FSAMPLE = 50 ksps 60 VDD = VREF = 5 V FSAMPLE = 100 ksps -40 -50 -60 -70 -80 -90 SINAD (dB) THD (dB) 50 40 30 20 VDD = VREF = 2.7 V FSAMPLE = 50 ksps VDD = VREF = 5V FSAMPLE = 100 ksps 1 10 100 10 0 -40 -35 -30 -25 -20 -15 -10 -5 0 -100 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency. FIGURE 2-24: Signal-to-Noise and Distortion (SINAD) vs. Input Signal Level. DS21298E-page 10 (c) 2008 Microchip Technology Inc. MCP3204/3208 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25C. 12.0 11.5 11.0 VDD = VREF = 5 V FSAMPLE =100 ksps 12.00 11.75 11.50 11.25 11.00 10.75 10.50 10.25 10.00 9.75 9.50 9.25 9.00 0.0 0.5 1.0 ENOB (rms) ENOB (rms) 10.5 10.0 9.5 9.0 8.5 8.0 VDD = VREF = 2.7 V FSAMPLE = 50 ksps VDD = VREF = 5 V FSAMPLE = 100 ksps VDD = VREF = 2.7 V FSAMPLE = 50 ksps 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VREF (V) 1 10 100 Input Frequency (kHz) FIGURE 2-25: (ENOB) vs. VREF. 100 90 80 Effective Number of Bits FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency. 0 VDD = VREF = 5 V FSAMPLE = 100 ksps Power Supply Rejection (dB) -10 -20 -30 -40 -50 -60 -70 -80 SFDR (dB) 70 60 50 40 30 20 10 0 1 10 100 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 1 10 100 1000 10000 Input Frequency (kHz) Ripple Frequency (kHz) FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10000 20000 30000 FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5000 10000 15000 Amplitude (dB) Amplitude (dB) VDD = VREF = 5 V FSAMPLE = 100 ksps FINPUT = 9.985 kHz 4096 points VDD = VREF = 2.7 V FSAMPLE = 50 ksps FINPUT = 998.76 Hz 4096 points 40000 50000 20000 25000 Frequency (Hz) Frequency (Hz) FIGURE 2-27: Frequency Spectrum of 10 kHz input (Representative Part). FIGURE 2-30: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V). (c) 2008 Microchip Technology Inc. DS21298E-page 11 MCP3204/3208 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25C. 500 450 400 350 VREF = VDD All points at FCLK = 2 MHz, except at VREF = VDD = 2.5 V, FCLK = 1 MHz 100 90 80 70 VREF = VDD All points at FCLK = 2 MHz except at VREF = VDD = 2.5 V, FCLK = 1 MHz IDD (A) IREF (A) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 300 250 200 150 100 50 0 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 2-31: 400 350 300 IDD vs. VDD. FIGURE 2-34: 100 90 80 IREF vs. VDD. VDD = VREF = 5 V VDD = VREF = 5 V 70 IREF (A) IDD (A) 250 200 150 100 50 0 10 100 1000 10000 VDD = VREF = 2.7 V 60 50 40 30 20 10 0 10 100 1000 10000 VDD = VREF = 2.7 V Clock Frequency (kHz) Clock Frequency (kHz) FIGURE 2-32: 400 350 300 IDD vs. Clock Frequency. FIGURE 2-35: 100 IREF vs. Clock Frequency. VDD = VREF = 5 V FCLK = 2 MHz 90 80 70 VDD = VREF = 5 V FCLK = 2 MHz IDD (A) IREF (A) 250 200 150 100 50 0 -50 -25 0 25 50 75 100 VDD = VREF = 2.7 V FCLK = 1 MHz 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 VDD = VREF = 2.7 V FCLK = 1 MHz Temperature (C) Temperature (C) FIGURE 2-33: IDD vs. Temperature. FIGURE 2-36: IREF vs. Temperature. DS21298E-page 12 (c) 2008 Microchip Technology Inc. MCP3204/3208 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25C. 80 2.0 Analog Input Leakage (nA) 70 60 VREF = CS = VDD 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 VDD = VREF = 5 V FCLK = 2 MHz IDDS (pA) 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) Temperature (C) FIGURE 2-37: 100.00 IDDS vs. VDD. FIGURE 2-39: Analog Input Leakage Current vs. Temperature. VDD = VREF = CS = 5 V 10.00 IDDS (nA) 1.00 0.10 0.01 -50 -25 0 25 50 75 100 Temperature (C) FIGURE 2-38: IDDS vs. Temperature. (c) 2008 Microchip Technology Inc. DS21298E-page 13 MCP3204/3208 NOTES: DS21298E-page 14 (c) 2008 Microchip Technology Inc. MCP3204/3208 3.0 PIN DESCRIPTIONS PIN FUNCTION TABLE MCP3208 PDIP, SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -- Symbol CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 DGND CS/SHDN DIN DOUT CLK AGND VREF VDD NC Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Digital Ground Chip Select/Shutdown Input Serial Data In Serial Data Out Serial Clock Analog Ground Reference Voltage Input +2.7V to 5.5V Power Supply No Connection Definition The descriptions of the pins are listed in Table 3-1. TABLE 3-1: MCP3204 PDIP, SOIC, TSSOP 1 2 3 4 -- -- -- -- 7 8 9 10 11 12 13 14 5, 6 3.1 Digital Ground (DGND) 3.5 Serial Data Input (DIN) Digital ground connection to internal digital circuitry. The SPI port serial data input pin is used to load channel configuration data into the device. 3.2 Analog Ground (AGND) 3.6 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. Analog ground connection to internal analog circuitry. 3.3 Analog Inputs (CH0 - CH7) Analog inputs for channels 0 - 7 for the multiplexed inputs. Each pair of channels can be programmed to be used as two independent channels in single-ended mode or as a single pseudo-differential input, where one channel is IN+ and one channel is IN. See Section 4.1 "Analog Inputs", "Analog Inputs", and Section 5.0 "Serial communications", "Serial Communications", for information on programming the channel configuration. 3.7 Chip Select/Shutdown (CS/SHDN) The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions. 3.4 Serial Clock (CLK) The SPI clock pin is used to initiate a conversion and clock out each bit of the conversion as it takes place. See Section 6.2 "Maintaining Minimum Clock Speed", "Maintaining Minimum Clock Speed", for constraints on clock speed. (c) 2008 Microchip Technology Inc. DS21298E-page 15 MCP3204/3208 NOTES: DS21298E-page 16 (c) 2008 Microchip Technology Inc. MCP3204/3208 4.0 DEVICE OPERATION 4.2 Reference Input The MCP3204/3208 A/D converters employ a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the fourth rising edge of the serial clock after the start bit has been received. Following this sample time, the device uses the collected charge on the internal sample/hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3204/3208. See Section 6.2 "Maintaining Minimum Clock Speed", "Maintaining Minimum Clock Speed", for information on minimum clock rates. Communication with the device is accomplished using a 4-wire SPI-compatible interface. For each device in the family, the reference input (VREF) determines the analog input voltage range. As the reference input is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D converter is a function of the analog input signal and the reference input, as shown below. EQUATION 4-1: 4096 x V IN Digital Output Code = -------------------------V REF Where: VIN VREF = = analog input voltage reference voltage 4.1 Analog Inputs When using an external voltage reference device, the system designer should always refer to the manufacturer's recommendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the operation of the A/D converter. The MCP3204/3208 devices offer the choice of using the analog input channels configured as single-ended inputs or pseudo-differential pairs. The MCP3204 can be configured to provide two pseudo-differential input pairs or four single-ended inputs, while the MCP3208 can be configured to provide four pseudo-differential input pairs or eight single-ended inputs. Configuration is done as part of the serial command before each conversion begins. When used in the pseudodifferential mode, each channel pair (i.e., CH0 and CH1, CH2 and CH3 etc.) is programmed to be the IN+ and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to (VREF + IN-). The IN- input is limited to 100 mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the IN+ and IN- inputs. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be FFFh. If the voltage level at IN- is more than 1 LSB below VSS, the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, then the FFFh code will not be seen unless the IN+ input level goes above VREF level. For the A/D converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. This diagram illustrates that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly effecting the time that is required to charge the capacitor (CSAMPLE). Consequently, larger source impedances increase the offset, gain and integral linearity errors of the conversion (see Figure 4-2). (c) 2008 Microchip Technology Inc. DS21298E-page 17 MCP3204/3208 VDD RSS CHx VT = 0.6V Sampling Switch SS RS = 1 k CSAMPLE = DAC capacitance = 20 pF VSS Legend VA Rss CHx Cpin Vt VA CPIN 7 pF VT = 0.6V ILEAKEAGE 1 nA = = = = = Signal Source Source Impedance Input Channel Pad Input Pin Capacitance Threshold Voltage Ileakage SS Rs Csample = = = = Leakage Current At The Pin Due To Various Junctions Sampling switch Sampling switch resistor Sample/hold capacitance FIGURE 4-1: Analog Input Model. 2.5 Clock Frequency (MHz) VDD = 5 V 2.0 1.5 1.0 VDD = 2.7 V 0.5 0.0 100 1000 10000 Input Resistance (Ohms) FIGURE 4-2: Maximum Clock Frequency vs. Input resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions. DS21298E-page 18 (c) 2008 Microchip Technology Inc. MCP3204/3208 5.0 SERIAL COMMUNICATIONS TABLE 5-1: Communication with the MCP3204/3208 devices is accomplished using a standard SPI-compatible serial interface. Initiating communication with either device is done by bringing the CS line low (see Figure 5-1). If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will determine if the conversion will be done using single-ended or differential input mode. The next three bits (D0, D1 and D2) are used to select the input channel configuration. Table 5-1 and Table 5-2 show the configuration bits for the MCP3204 and MCP3208, respectively. The device will begin to sample the analog input on the fourth rising edge of the clock after the start bit has been received. The sample period will end on the falling edge of the fifth clock following the start bit. Once the D0 bit is input, one more clock is required to complete the sample and hold period (DIN is a "don't care" for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 12 clocks will output the result of the conversion with MSB first, as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 12 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 "Using the MCP3204/3208 with Microcontroller (MCU) SPI Ports" for more details on using the MCP3204/3208 devices with hardware SPI ports. CONFIGURATION BITS FOR THE MCP3204 Channel Selection CH0 CH1 CH2 CH3 CH0 = IN+ CH1 = INCH0 = INCH1 = IN+ CH2 = IN+ CH3 = INCH2 = INCH3 = IN+ Input Configuration Single/ D2* D1 D0 Diff 1 1 1 1 0 0 0 0 X X X X X X X X 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 single-ended single-ended single-ended single-ended differential differential differential differential Control Bit Selections * D2 is a "don't care" for MCP3204 TABLE 5-2: Control Bit Selections Single /Diff 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CONFIGURATION BITS FOR THE MCP3208 Input Configuration 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 single-ended single-ended single-ended single-ended single-ended single-ended single-ended single-ended differential differential differential differential differential differential differential differential Channel Selection CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH0 = IN+ CH1 = INCH0 = INCH1 = IN+ CH2 = IN+ CH3 = INCH2 = INCH3 = IN+ CH4 = IN+ CH5 = INCH4 = INCH5 = IN+ CH6 = IN+ CH7 = INCH6 = INCH7 = IN+ D1 D0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 (c) 2008 Microchip Technology Inc. DS21298E-page 19 MCP3204/3208 tCYC tCSH CS tSUCS CLK tCYC DIN Start DIFF D2 SGL/ D1 D0 Don't Care Start SGL/ D2 DIFF DOUT HI-Z Null Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* tCONV tSAMPLE tDATA ** HI-Z * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB first data, followed by zeros indefinitely (see Figure 5-2 below). ** tDATA: during this time, the bias current and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. FIGURE 5-1: Communication with the MCP3204 or MCP3208. tCYC CS tSUCS CLK Start DIN D2 D1 D0 SGL/ DIFF Don't Care tCSH Power Down DOUT HI-Z * Null B11B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11 Bit HI-Z (MSB) tSAMPLE tCONV tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out LSB first data or zeroes. FIGURE 5-2: Communication with MCP3204 or MCP3208 in LSB First Format. DS21298E-page 20 (c) 2008 Microchip Technology Inc. MCP3204/3208 6.0 6.1 APPLICATIONS INFORMATION Using the MCP3204/3208 with Microcontroller (MCU) SPI Ports With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Because communication with the MCP3204/3208 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending `leading zeros' before the start bit. As an example, Figure 6-1 and Figure 6-2 illustrate how the MCP3204/ 3208 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the `low' state, while Figure 6-2 shows the similar case of SPI Mode 1,1, where the clock idles in the `high' state. CS MCU latches data from A/D converter on rising edges of SCLK SCLK 1 2 3 4 5 6 7 8 9 10 11 12 As is shown in Figure 6-1, the first byte transmitted to the A/D converter contains five leading zeros before the start bit. Arranging the leading zeros this way allows the output 12 bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D converter on the falling edge of clock number 12. Once the second eight clocks have been sent to the device, the MCU's receive buffer will contain three unknown bits (the output is at high impedance for the first two clocks), the null bit and the highest order four bits of the conversion. Once the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Employing this method ensures simpler manipulation of the converted data. Figure 6-2 shows the same thing in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the A/D converter outputs data on the falling edge of the clock and the MCU latches data from the A/D converter in on the rising edge of the clock. 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D converter on falling edges DIN SGL/ Start DIFF D2 D1 DO Don't Care Don't Care DOUT HI-Z NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Start Bit MCU Transmitted Data SGL/ SGL/ D2 (Aligned with falling 0 0 0 0 0 1 DIFF D2 DIFF edge of clock) MCU Received Data (Aligned with rising ? ? ? ? ? ? ? ? edge of clock) Data stored into MCU receive register after transmission of first X = "Don't Care" Bits 8 bits D1 DO D1 DO ? ? ? ? X X X X X X X X X X X X X X 0 B11 B10 B9 B8 ? 0 ? (Null) B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). (c) 2008 Microchip Technology Inc. DS21298E-page 21 MCP3204/3208 CS MCU latches data from A/D converter on rising edges of SCLK SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D converter on falling edges DIN HI-Z Start Bit Start DIFF SGL/ D2 D1 DO Don't Care DOUT NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 MCU Transmitted Data (Aligned with falling 0 edge of clock) MCU Received Data (Aligned with rising edge of clock) ? 0 ? 0 ? 0 ? 0 ? 1 SGL/ D2 DIFF D1 DO X X X X X X X X X X X X X X ? ? ? ? ? 0 ? (Null) B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive register after transmission of last 8 bits X = "Don't Care" Bits Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). 6.2 Maintaining Minimum Clock Speed 6.3 When the MCP3204/3208 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample capacitor while the conversion is taking place. At 85C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2 ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2 ms (effective clock frequency of 10 kHz). Failure to meet this criterion may introduce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met. Buffering/Filtering the Analog Inputs If the signal source for the A/D converter is not a low impedance source, it will have to be buffered or inaccurate conversion results may occur (see Figure 4-2). It is also recommended that a filter be used to eliminate any signals that may be aliased back into the conversion results, as is illustrated in Figure 6-3, where an op amp is used to drive the analog input of the MCP3204/3208. This amplifier provides a low impedance source for the converter input, and a low pass filter, which eliminates unwanted high frequency noise. Low-pass (anti-aliasing) filters can be designed using Microchip's free interactive FilterLab(R) software. FilterLab will calculate capacitor and resistor values, as well as determine the number of poles that are required for the application. For more information on filtering signals, see AN699, "Anti-Aliasing Analog Filters for Data Acquisition Systems". DS21298E-page 22 (c) 2008 Microchip Technology Inc. MCP3204/3208 VDD 4.096V Reference 0.1 F MCP1541 1 F IN+ VREF MCP3204 R1 C1 R2 C2 R3 R4 MCP601 + IN1 F 10 F VIN FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a second order anti-aliasing filter for the signal being converted by the MCP3204. 6.4 Layout Considerations When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device, placed as close as possible to the device pin. A bypass capacitor value of 1 F is recommended. Digital and analog traces should be separated as much as possible on the board, with no traces running underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a "star" configuration can also reduce noise by eliminating return current paths and associated errors (see Figure 6-4). For more information on layout tips when using A/D converters, refer to AN688, "Layout Tips for 12-Bit A/D converter Applications". Device 1 VDD Connection Device 4 Device 3 Device 2 FIGURE 6-4: VDD traces arranged in a `Star' configuration in order to reduce errors caused by current return paths. (c) 2008 Microchip Technology Inc. DS21298E-page 23 MCP3204/3208 6.5 Utilizing the Digital and Analog Ground Pins The MCP3204/3208 devices provide both digital and analog ground connections to provide another means of noise reduction. As shown in Figure 6-5, the analog and digital circuitry is separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the substrate, which has a resistance of 5 -10. If no ground plane is utilized, then both grounds must be connected to VSS on the board. If a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be connected to the analog ground plane. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D converter. VDD MCP3204/08 Digital Side -SPI Interface -Shift Register -Control Logic Analog Side -Sample Cap -Capacitor Array -Comparator Substrate 5 - 10 DGND AGND 0.1 F Analog Ground Plane FIGURE 6-5: Separation of Analog and Digital Ground Pins. DS21298E-page 24 (c) 2008 Microchip Technology Inc. MCP3204/3208 7.0 7.1 PACKAGING INFORMATION Package Marking Information 14-Lead PDIP (300 mil) (MCP3204) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example: MCP3204-B I/P e3 0819256 14-Lead SOIC (150 mil) (MCP3204) Example: XXXXXXXXXXX XXXXXXXXXXX YYWWNNN MCP3204-B I/SL e3 XXXXXXXI/XXXX 0819256 14-Lead TSSOP (4.4mm)* (MCP3204) Example: XXXXXXXX YYWW NNN 3204-C 0819 256 Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2008 Microchip Technology Inc. DS21298E-page 25 MCP3204/3208 Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3208) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example: MCP3208-BI/P e3 0819256 16-Lead SOIC (150 mil) (MCP3208) Example: XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN MCP3208-B I/SL e3 XXXXIXXXXXX 0819256 DS21298E-page 26 (c) 2008 Microchip Technology Inc. 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DS21298E-page 31 MCP3204/3208 /HDG 3ODVWLF 6PDOO 2XWOLQH 6/ 1DUURZ 1RWH PP %RG\ >62,&@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E1 NOTE 1 1 2 b 3 e E h h c A A2 A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK &KDPIHU RSWLRQDO )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ ( ( ' K / / I F E D E 0,1 0,//,0(7(56 120 %6& %6& %6& %6& 5() 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & PP SHU VLGH % DS21298E-page 32 (c) 2008 Microchip Technology Inc. MCP3204/3208 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ (c) 2008 Microchip Technology Inc. DS21298E-page 33 MCP3204/3208 NOTES: DS21298E-page 34 (c) 2008 Microchip Technology Inc. MCP3204/3208 APPENDIX A: REVISION HISTORY Revision E (September 2008) The following is the list of modifications: 1. Updated package outline drawings Section 7.0 "Packaging Information". in Revision D (January 2007) The following is the list of modifications: 1. Undocumented changes Revision C (May 2002) The following is the list of modifications: 1. Undocumented changes Revision B (August 1999) The following is the list of modifications: 1. Undocumented changes Revision A (November 1998) * Initial release of this document. (c) 2008 Microchip Technology Inc. DS21298E-page 35 MCP3204/3208 NOTES: DS21298E-page 36 (c) 2008 Microchip Technology Inc. MCP3204/3208 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -X Grade X /XX Examples: a) MCP3204-BI/P: 1 LSB INL, Industrial Temperature, PDIP package. 1 LSB INL, Industrial Temperature, SOIC package. 2 LSB INL, Industrial Temperature, TSSOP package. 1 LSB INL, Industrial Temperature, PDIP package. Temperature Package Range Device MCP3204: 4-Channel 12-Bit Serial A/D Converter MCP3204T: 4-Channel 12-Bit Serial A/D Converter (Tape and Reel) MCP3208: 8-Channel 12-Bit Serial A/D Converter MCP3208T: 8-Channel 12-Bit Serial A/D Converter (Tape and Reel) B C I P SL ST = 1 LSB INL = 2 LSB INL = -40C to +85C (Industrial) b) MCP3204-BI/SL: c) MCP3204-CI/ST: Grade: a) MCP3208-BI/P: Temperature Range Package b) = Plastic DIP (300 mil Body), 14-lead, 16-lead = Plastic SOIC (150 mil Body), 14-lead, 16-lead = Plastic TSSOP (4.4mm), 14-lead MCP3208-BI/SL: 1 LSB INL, Industrial Temperature, SOIC package. MCP3208-CI/ST: 2 LSB INL, Industrial Temperature, TSSOP package. c) (c) 2008 Microchip Technology Inc. DS21298E-page 37 MCP3204/3208 NOTES: DS21298E-page 38 (c) 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2008 Microchip Technology Inc. DS21298E-page 39 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 01/02/08 DS21298E-page 40 (c) 2008 Microchip Technology Inc. |
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